A desynchronizer is a device that reads and transmits asynchronous data carried over a synchronous channel. A synchronizer is used in conjunction with a desynchronizer and is allocated sufficient bandwidth over the synchronous channel to carry the maximum data rate with control signals being used to indicate the amount of data actually contained within the synchronous channel. Excess bandwidth is used for asynchronous data within the synchronous channel and is filled with bits carrying no information, or stuff bits. A pointer adjustment technique may be used in lieu of, or in addition to, stuff bits to indicate changes in the data rate of the synchronous channel. The synchronous channel also contains additional data, known as overhead, in addition to the asynchronous payload data. The variations in the instantaneous rate of the payload data caused by the interspersing of this overhead data and the stuff bits or pointer adjustments can give rise to what is called payload mapping jitter which can feed through into the desynchronizer output.
Conventional desynchronizers have typically included a first in first out (FIFO) buffer, a phase detector to measure the FIFO buffer depth, a passive or active analog loop filter to filter the phase detector output, and a voltage controlled oscillator (VCO) to generate an output clock to control data transmission from the FIFO buffer. These elements make up a phase locked loop (PLL) traditionally used in desynchronizers. The mapping jitter due to instantaneous variations in the FIFO buffer depth must be filtered within a PLL circuit often requiring undesirable compromises in the loop response. The phase locked loop circuit is usually implemented as an analog design, though replacement of one or more of these sections with digital circuitry is practical in many cases.
The purpose of the PLL circuit is to keep the FIFO buffer at a constant depth, typically half full. The FIFO buffer depth is filtered and used to drive the PLL circuit in order to control the clock frequency of the VCO used to read data from the FIFO buffer. Extra data written into the FIFO buffer is reflected on the clock signal of the VCO such that data is read out from the FIFO buffer a little faster to bring the FIFO buffer depth back to its nominal level. Less data causes the VCO to generate a slower clock signal, slowing down data transmission from the FIFO buffer and maintaining a nominal FIFO buffer depth. Instantaneous variations in the FIFO buffer depth filter through the PLL circuit, causing mapping jitter to appear on the desynchronizer output.
To avoid overflow and underflow of the FIFO, a PLL desynchronizer has feedback which must compensate for unavoidable variations in phase detector, loop filter, and VCO characteristics. Both analog and digital PLL designs require that the phase detector, loop filter, and VCO be well characterized and stable for proper dynamic performance of the desynchronizer. Shifts in the characteristics of these elements may result in excessive overshoot in the PLL step response, leading to jitter amplification and other undesirable effects. It is therefore desirable to eliminate mapping jitter feed-through and excessive overshoot in the PLL step response and simplify the circuitry as compared to conventional PLL desynchronizer designs.
From the foregoing it may be appreciated that a need has arisen for a desynchronizer that eliminates mapping jitter feedthrough into the desynchronizer output normally found in conventional desynchronizer designs due to the variations in the instantaneous rate of the FIFO buffer depth. A need has also arisen for a desynchronizer that eliminates overshoot from the desynchronizer step response and eliminates gain in the jitter transfer function. Further, a need has arisen for a simplified desynchronizer design which avoids feedback problems found in conventional PLL desynchronizer designs.